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Problems in Implementing practical Brain Machine Interfaces. A short overview

In institutions and homes throughout the world there are countless thousands of individuals who are held prisoner by their bodies. Unable to interact with their environment due to stroke or accident, and yet behind those eyes are rational and fully sentient individuals, who probably to the last person would offer up their life to advance science in its quest to free them from their terrible bonds. It is equally true that to offer a false hope to them with a technology that is not ready, is even a more unspeakable cruelty. In regards to brain machine interfaces it may be a long road from Spider Monkeys to Man or only a brief journey. Technology has made tremendous strides in the recent past and it is now possible to consider the possibility that the day of practical and workable brain machine interfaces are now a realizable goal. A goal that is achievable, not in 20 years or even 10 years, but much, much sooner. It is important to remember that for a person who has no movement, the ability to move a single finger represents tremendous opportunity, to move five fingers a chance at relative independence and even without movement, the ability to navigate in cyberspace a new life filled with hope and joy with the prospects of a new day.

The use of an existing IC technology offers the promise of greatly accelerating the time scale in which the advanced goals of Brain Machine Interfaces may be achieved. The application of this technology will allow direct measurement of brain activity with tens of thousands of detectors per IC. Signal processing systems with virtually unlimited signal density are conceivable and practical. With modification the same technology allows for the addition of stimulation thereby closing the loop between measurement and action.

What would be the properties of the ideal Brain Machine Interface?

From a laboratory perspective the interface should be small, light weight, easy to use and interface to the brain and relatively free of irritating quirks. It should be approachable as any other standard piece of test equipment. It would be essentially, an IC test station not unlike that found in any IC production environment, capable of both stimulating and measuring a multitude of signals. The goal is clear, simply take your standard Pentium Processor test station and reduce its size, weight, and cost by 4 orders of magnitude while at the same time increasing the signal density by a similar amount.

From a user perspective the brain machine interface should weigh, including batteries, no more than 20 lbs., be relatively free of maintenance, not offer a site for infection, and allow free and unencumbered use for extended periods of time.

The brain is by its nature both a highly distributed and highly specific in its architecture. It is well known that if some portion of the brain should be injured other areas will take over and perform the lost functions, the younger the organism the more likely the phenomena. Likewise, patients will report vastly different perceptions, sensations, memories, under brain stimulation with the stimulating electrode moved even tiny distances. Thus there is a need for both a regional and specific viewpoint. It will be interesting to discover if the brain will accept a BMI as part of itself and integrate the mechanism into the brain network. It would seem that a device that provides a stimulus much like a sensory organ would be a necessary component for this effect to occur.

The central problem in making and constructing usable brain machine interfaces is not the electronics. As will be discussed later in this paper detector ICs with 10’s of thousands of detectors are practical today. Concepts, no matter how complex, can always be reduced in size and weight to accomplish the mission profile. If more processing power is required then a means will be defined to make it possible. This problem existed 50 years ago, exists today, and will no doubt exist far into the future. The interface between the machine and the brain is by definition an electrode. We will exclude for the moment H field induced phenomena that no doubt need further investigation. The electrode is the device that takes ionic flow existing within a cell, and as a result of biological membrane potentials and converts that ionic flow into electrons. There are only a small handful of materials suitable for electrodes, principally the noble medals and stainless steel. For measurement electrodes there is really only one choice, Ag/AgCl. That’s it. There are no other viable choices. Never the less, the technology to be proposed will support the development of dry, non-ionic electrodes as one of the methodologies if required.

The engineering perspective of the ideal brain machine interface is different. While keeping in mind that size, weight, utility, and ease of use play an important role in defining the properties of a BMI, the engineer is concerned with making the process work. From electrodes, through the preamplifiers, onto intermediate signal processors, gain, DSPs, FPGAs, code, …….

BMIs have a unique property that make them unique in science. Specifically, it is open ended. The size, complexity, and processing power necessary to successfully accomplish the objective are all unknown. Since the science is for the most part unknown and ill defined, it is to the engineers advantage to design his tools in a way that is not self limiting.

Solutions:

Cybin Labs proposes to use existing CMOS multiplexer technology as the front end for a state of the art defining brain machine interface. CMOS multiplexer technology is presently used in Indium Antimonide IR sensors. In their IR application the multiplexers integrate photon-generated charge produced in a photo diode over an integration period lasting from 10s to hundreds of microseconds. At the end of each integration period the accumulated charges are transferred to an analog shift register and output as a stream of analog samples. Normally the detectors are located in a cryogenically cooled Dewar cooled to 76 °K. After the signals leave the Dewar they are buffered and sampled by video rate A/D converters. In the multiplexer which this author has direct experience there are 8 channels made up of 12 rows of 240 detectors each. Giving a total of

8 x 240 x 12 = 23,040 detectors/ multiplexer. The pitch of the detectors are 10 microns.

Present multiplexers do not have significant drive capability to minimize heat load on the Dewar Cryo cooler. In this application additional drive electronics may be desirable. It will also be necessary to change the multiplexer front end to accommodate a difference in sensor types. Of course the multiplexers will function at body temperature rather than at liquid N2 temperatures.

Rather than join the CMOS multiplexer to the In/Sb substrate, in a process known as hybridization, it is proposed to replace the In/Sb substrate with a sapphire or ceramic substrate in which the necessary electrodes have been deposited. The signal bandwidths are easily within the limits typical for the brain. Power consumption is low, amounting to a few 10s of milliwatts per IC.

Since this is an existing technology for which there is considerable experience it is likely that the time from concept to working prototype could be very short, perhaps less than 8 months. This delay is mostly a result of scheduling the designer and arranging for foundry time.

Multiple variations of electrode arrays are possible including simple arrays deposited onto sapphire to more complex nets whose methods of fabrication yet remain to be determined. As always, the electrodes remain a significant problem separate from the detector electronics.

A necessary component of the array signal processing is the implementation of a two point correction for gain and offset which will exist at each electrode. The two point correction follows pre-amplification but precedes any and all further signal processing. Present day designs convert the signal to a digital form immediately after the multiplexer gain stage. Thus the 2-point correction is only the first operation to be performed on a now digital signal. Even though the bandwidths of a single channel may be relatively low, lets say 1 KHz, certainly a practical bandwidth for cortical measurements, when multiplied by the channel densities practical to consider, say 10 thousand channels per IC the computational burden quickly explodes. So that’s another factor of 5 to satisfy the Nyquist criteria giving 50 MHz signal processing bandwidth per IC. Using the best video rate A/D converters gives 14 bits/sample or 700 Mbits/second/IC. Let’s push the envelope a bit further and say that we’re to deploy an array of 16 detector nodes spread over various sensory and motor cortexes. This gives a raw throughput processing goal of 11.2 Gbits/sec. Seems reasonable, and using the right technology achievable within the 20 lb. system weight requirement. Actually, this component should fit with a 3 lb. weight limit since we need batteries, a belt to hold them, etc. So off the data goes to a really fast signal processor. Running arbitrary algorithms of unknown complexity with unknown speed requirements. And remember, if it isn’t real time … Don’t bother!

The proposed array signal processor architecture is highly dependant upon FPGA technology. Each signal processing node in the system utilizes a common signal interface specifically designed to move data at extremely high data rates. Present day FPGA technology allows for a 1024 complex FFTs to be accomplished in approximately 1 ms. Thus, 1 m /1024 point FFT X 160,000 channels = 6.25 data frames/s. Using the previous computational burden as an example, the entire processing load could be accomplished with only a single Xilinx Vertex II FPGA. While the FFT is certainly not the solution it does illustrate that technology has made tremendous progress. The signal processing architecture supports multiple devices connected in arbitrary architectures with arbitrary algorithms. With the exception of a few specific devices such as RF modulators

What should be immediately apparent is that data presentation and interpretation is a significant problem. The development of goal directed algorithms which can arrive at a solution independent of human bias represent perhaps, the most significant problem.

Schedule:

Estimated costs are as follows:

IC multiplexer design $80,000

Prototype testing $20,000

Production run of 100 8” wafers $250,000

Electrode design and fabrication $35,000

IC handling equipment, Including slicers, probers, hybridyzers, clean room facilities,

$525,000

Laboratory space, $60,000/year

FPGA design software $45,000/seat

Engineering support staff, secretarial services, $100,000/year

PCB Design and FAB overhead & salary $120,000 /engineer year

Engineering overhead & salary $180,000/engineer year. 3 required 1 mechanical, 2 electrical

Plant overhead Power, water, phone, network access $10,000/year

Program Manager overhead & salary $240,000 /engineer year